1. Field of the Invention
This invention relates to semiconductor memory systems and particularly to information sense amplifiers for single FET/capacitor memory cells.
2. Description of the Prior Art
U.S. Pat. No. 3,387,286 entitled "Field Effect Transistor Memory", issued June 4, 1968, to R. H. Dennard and assigned to the present assignee, describes an array of semiconductor memory cells, each comprising only a single FET coupled to a storage capacitor. Because of the relatively lower cost of FET processing over bipolar processing and the inherent optimum density achievable using a single active device in a memory cell, the approach to designing high density semiconductor memory systems has, in recent years, emphasized the development of single FET/capacitor memory cell technology.
A typical sense amplifier and memory system configuration for such memory cells appears in U.S. Pat. No. 3,678,473 entitled "Read-Write Circuit for Capacitive Memory Arrays", issued July 18, 1972, to S. E. Wahlstrom, which includes a ratioless cross-coupled sense latch coupled between common bit lines of a pair of single FET/capacitor memory arrays. A charged or uncharged memory capacitor is coupled to one bit line and a reference potential is coupled to the other bit line, the differential potential between the bit lines is sensed. In large memory systems where the parasitic capacitance of the bit/sense line is large compared with the storage capacitance, the sense signal is severely attenuated due to the charge redistribution between the small storage capacitance and the large bit/sense line capacitance. In practical FET devices any imbalances, such as differences in the threshold voltages of the cross-coupled devices, or differences in bit line capacitance, requires that a sense signal larger than the minimum achievable through cell design be provided to offset any mismatch. In addition, the speed at which the latch can be set is limited by the size of the bit/sense line capacitance which must be driven to high and low signal levels. The article, "Sense Latch Circuit for Memory Cells", by A. Furman et al. IBM Technical Disclosure Bulletin, February 1974, pp. 2792-3, provides clock driven isolation devices between the latch sense nodes and the bit/sense lines to isolate the bit/sense line capacitance from the latch circuit at the time the latch is being set.
Additional improvements in sense amplifier design are taught in U.S. Pat. No. 3,764,906 entitled "Stored Charge Detection by Charge Transfer", issued Oct. 9, 1973, to L. G. Heller and assigned to the instant assignee, which teaches a charge transfer, or bucket brigade, sensing technique which is insensitive to device parameters and can effectively transfer the storage capacitor voltage directly to the sense node. This technique, although more sensitive to input voltages, is slower than the dynamic latch due to the time required to fully charge the large bit/sense line capacitance through an FET approaching cutoff while operating in the saturation region. Improvements in charge transfer sense amplifiers are found in U.S. Pat. No. 3,760,381, entitled "Stored Charge Memory Detection Circuit", issued Sept. 18, 1973, to Y. L. Yao and assigned to the instant assignee, and in the article "Differential Sense Amplifier" by D. P. Spampinato, IBM Technical Disclosure Bulletin, November 1974, pp. 1797-8.
In summary, two different types of sense amplifiers have been previously proposed for use with single FET/capacitor memory cells. The dynamic cross-coupled latch, although faster, remains device parameter sensitive and therefore requires a larger input signal, while the charge transfer sense amplifier is more sensitive but slower.
Three additional prior art references are pertinent to certain aspects of the subject invention and, although they relate to diverse areas of the semiconductor art, are described below:
U.S. Pat. No. 3,549,912, entitled "JK Flip-Flop", issued Dec. 22, 1970 to R. G. Lewis, describes a bipolar flip-flop circuit which uses a capacitively coupled clock signal combined with pulse steering diodes to disable the conductive one of a pair of cross-coupled transistors in order to allow the static state of the flip-flop to be more quickly changed.
The article, "Sense Amplifier for IGFET Memory", by D. L. Critchlow, IBM Technical Disclosure Bulletin, November 1970, pp. 1720-2, shows a cross-coupled FET sense/latch circuit in which the source electrodes of the cross-coupled FETs are coupled to separate voltage nodes from which an output signal is derived. The nodes are initially unconditionally prebiased to the same DC potential.
U.S. Pat. No. 3,854,059, entitled "Flip-Flop Circuit", issued Dec. 10, 1974, to K. Nomiya et al., shows an FET flip-flop in which cross-coupled devices, having isolated source electrodes, are initially precharged. The circuit also includes separate source pull-down devices for each of the cross-coupled FET devices. In operation the circuit is responsive to logical input signals selectively applied to the precharged source nodes prior to activation of the source pull-down devices. Regenerative operation is prevented by a feedback interrupting device conditioned to be conductive only during a precharge period.